1. Field of the Invention
The present invention relates to a logic simulation apparatus.
2. Description of the Related Art
In recent years, with an increase in scale of an LSI and complications thereof, various CAD systems have been utilized in the designing process of LSI. In an architecture design or a logic circuit design, a designer often describes the internal structure or operation of a circuit module using a hardware description language. As the hardware description language, VHDL or the like is a typical example. In order to verify that the description of a circuit is correct, simulation is frequently performed using a logic simulation apparatus to check whether an expected result is obtained. As this logic simulation apparatus, a batch simulator for executing simulation at a high speed up to designated or specified time or an interactive simulator which has a speed lower than that of the batch simulator but is convenient to debug is known.
The logic simulation apparatus executes simulation program to perform simulation. The simulation program mainly has procedures for elaboration, procedures for simulation, and procedures for handling events (FIG. 1). As other procedures executed on the logic simulation apparatus, various procedures such as a procedure for check point, a procedure for a page-in/page-out, and a procedure for user interface are known.
Means for verifying a circuit by simulation using the logic simulation apparatus is very effective. However, a considerably long time is required for executing the simulation. This is a large factor for preventing from shortening a design time.
As the reason why the simulation is executed at a low speed, the low speed of check point process is known. In the check point process, a circuit state (data indicating the circuit state) in the execution process of the simulation is stored in a disk apparatus or the like at a predetermined timing, and the simulation is restarted from the stored state. The check point process is effective in the following cases.
(i) During simulation whose execution requires several days, even if the latest state of the simulation is lost due to a power failure or breakdown of an apparatus, the simulation from the beginning need not be restarted. PA1 (ii) Even if a circuit state becomes in a different state from an expected value during execution of simulation, a state obtained immediately before the circuit is set in this state can be rapidly reproduced to specify an erroneous portion of a circuit design. PA1 (iii) In various tests performed to a circuit subjected to simulation from the desired intermediate state, the desired intermediate state is saved by the check point process, so that the simulation again from an initial state to the intermediate state can be omitted in each test.
In order to execute simulation of the circuit described above by VHDL or the like, the entire structure of the circuit subjected to simulation is constituted by a partial circuit (i.e., a circuit module) described by the VHDL. This process is called elaboration process. A conventional elaboration process is performed as follows.
With respect to circuit modules corresponding to an entire circuit subjected to simulation, signals defined in the circuit modules, data representing registers, pointer information indicating lower-level circuit modules, and the like are stored in a storing device. The same processes as described above are performed to the lower-level circuit modules of the circuit modules. When the hierarchy of a circuit description is developed from upper-level circuit modules to lower-level circuit modules by the same sequence as described above, data areas corresponding to the circuit modules are sequentially allocated in the storing device.
According to a conventional logic simulation apparatus, as a result of the elaboration process, as shown in FIG. 2, when the entire circuit is divided into a plurality of circuit blocks, information relating to one circuit block is stored in adjacent areas in the storing device, and pieces of information of circuit blocks l, m, and n having a close relationship (e.g., upper-level, lower-level, and same-level) in a hierarchical structure are stored adjacent areas.
As check point process of information relating to a conventional circuit block, a process for saving entire data of a circuit subjected to the simulation as shown in FIG. 2, or a process for searching and saving only variable data which changes depending on a signal or simulation time of a register while modules are sequentially traced is performed. In the former, since the amount of data to be saved becomes very large, not only check point process requires a long time, but also a storing capacity required for saving the data disadvantageously increases. Although the latter is often used to save the storing capacity, in this case, the process speed of simulation decreases because a long time is required for performing search process of a data portion which must be saved.
As another reason why simulation is executed at a low speed, a page-out process requires a long time. The page-out process is a process for temporarily paging out part of the storing device which is in use to a magnetic disk device or the like using one page as a unit so as to execute, e.g., another job having a high priority. In this page-out process, when a page to which a page-out process has been performed is not updated after a previous page-out process is required, if a page-out process is performed, the contents of the page need not be written in the disk device again because the same data as that of the page to which page-out process has been performed is saved in the disk device. In a conventional elaboration, since pieces of information which change during the execution process of simulation are distributed as described above, a page to which a page-out process has been performed is updated at a very high probability after the previous page-out process is performed, and the contents of the page must be frequently written in the disk device. For this reason, the speed of the page-out process decreases, thereby delaying execution of the simulation.
With respect to simulation, in addition to high-speed processing, another serious problem is posed. In a conventional simulator, since data representing the state of a circuit has a large capacity of several Mbytes, pointer information used as the above circuit information requires data having a capacity of about 4 bytes. For this reason, a total storing capacity required for all pointers disadvantageously becomes very large.
As described above, as the logic simulation apparatus, a batch simulator for executing simulation at a high speed up to designated time or an interactive simulator which has a speed slightly lower than that of the batch simulator but is convenient to debug is known.
When circuit is to be verified, simulation is executed up to time T, and debugging is performed from time T. As a method of performing the debugging, the following two methods are known. The first method is a method in which an interactive simulator is used from the beginning. However, the first method has a problem that a long time is required to execute the simulation up to time T. The second method is as follows. That is, simulation is executed by the batch simulator up to time T, a circuit state (data indicating this) obtained at time T stored inside the simulator is dumped in a file, an interactive simulator is activated, and the file is loaded, thereby restarting the simulation. According to this method, a long time is required for reading and writing data from/in the file.
With respect to simulation program, trade-off is established between simulation speed and a time from when a circuit description is changed to when simulation is started. For example, in compiled simulator, when the simulator is complied without optimization, the compile time tends to be short but the simulation speed tends to be low. However, when it is compiled with optimization, the time tends to be long but the simulation speed tends to be high. In general, when simulation is started again from the beginning by changing the circuit description, an error may occur immediately after the simulation is started, or an error may occur after the simulation is executed for a considerably long time. For this reason, time at which an error occurs for the first time after the simulation is started is not always recognized before the simulation is started. Therefore, it cannot be correctly determined whether the simulator having a short time required for starting the simulation or the simulator having high simulation speed must be selected to reach time at which an error occurs for the first time.
During simulation, as debugging means, for example, showing the circuit state such as the structure of the circuit or the signal value to display means or the like is used. This function is conventionally realized by two methods. The first method is a method of installing a procedure for displaying the state in the simulator. According to this method, since the procedure is always set even when the procedure is not necessary, a program size disadvantageously increases. The second method is a method of developing a display program to transfer data to the display program through a file. According to this method, since a long time is required for reading/writing data from/in the file, a time from when a display operation is requested by a user to when the data is actually displayed is disadvantageously long.
As described above, in a conventional logic simulation apparatus, since a long time is required for check point process and a page-out process, these processes make the simulation speed low. In addition, the conventional simulation apparatus disadvantageously requires a large information amount for each pointer.
In the conventional logic simulation apparatus, an interactive simulator itself has a low simulation speed. In a method of simulation such that a batch simulator is switched to an interactive simulator during the simulation to increase the simulation speed, a long time is disadvantageously required for switching the batch simulator to the interactive simulator.
In the conventional logic simulation apparatus, simulation speed is low when a required time from when the circuit description changes to when the simulation is started, and the simulation speed is high when the required time is long. A simulator having the shortest time required for detecting an error is not always selected.
In addition, according to the conventional logic simulation apparatus, in a method of displaying a circuit state, an excellent response cannot be easily realized by using a small memory amount because trade-off is established between the required memory amount and the response to a request from a user.